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ISL5586
TM
Data Sheet
June 2001
File Number
4924.1
Low Power Ringing SLIC for Home Gateways
The ISL5586 is a very low power Ringing Subscriber Interface circuit designed for use with the Broadcom* BCM3352 Cable Modem Chip, with on-board voiceband codecs, or other 3.3V voiceband codec devices. The ISL5586 provides on board ringing signal generation up to 95V peak supporting sinusoidal or trapezoidal waveshapes with DC offset. Loop start and ground start trunks are supported, and an open circuit DC voltage of less than 56V is maintained on the subscriber loop in the on-hook condition, in compliance with MTU operation and the safety requirements of UL-1950. Together with the Broadcom BCM3352, the ISL5586 provides resistive and complex two wire impedance matching and transhybrid balancing. Also supported are onhook transmission of caller id signals, soft and hard polarity reversal and 12/16kHz subscriber pulse metering systems used in Europe and Asia, thereby allowing a low cost, low risk, global product design to be achieved.
Features
* Interfaces to Broadcom 3352 cable modem device * Very low on-hook power consumption - 64mW @ Vbh = 75V * User Programmable constant current to the subscriber loop * On Chip ring generation - Balanced to 95 Vpk * Sinewave, Trapezoid, DC offset * Programmable loop start and ring trip detectors * Loop start, Ground Start, Polarity Reversal (soft/hard) * On-Hook transmission and pulse metering support * Integrated battery switch * Open circuit line voltage clamp * Compatible with 3.3V devices * TR-57 compliant Longitudinal balance * 28 PLCC packaging * Latch-up free Bipolar design * Thermal protection
Applications
* * * * * * * Cable Modems Voice Over DSL (VoDSL) Broadband Wireless Access Voice Over Internet Protocol (VoIP) ISDN Terminal Adapters (TA) Small Office Home Office PBX Wireless Local Loop
Related Literature
* Evaluation Board for the ISL5586 family AN9918 * Technical Brief TB363 "Guidelines for Handling and Processing Moisture Sensitive Surface Mount Devices (SMDs)"
Block Diagram
POL CDCP CDCM DC CONTROL VBL VBH BATTERY SWITCH
ILIM
RINGING PORT
VRSP VRSM
TIP RING
2-WIRE PORT TRANSIENT CURRENT LIMIT TRANSMIT SENSING 4-WIRE PORT
VRXP VRXM -IN VZO VFB VTXP VTXM F2 F1 F0
TL
INTERNAL LOOP BACK
DETECTOR LOGIC
CONTROL LOGIC
RTD RD
DET
BSEL
*Broadcom is a registered trademark of Broadcom Corp.
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RSLIC18TM is a trademark of Intersil Corporation. CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil and Design is a trademark of Intersil Americas Inc. Copyright (c) Intersil Americas Inc. 2001, All Rights Reserved
ISL5586 Ordering Information
HIGH BATTERY (VBH) PART NUMBER ISL5586FCM ISL5586BIM ISL5586CIM ISL5586DIM 100V 85V 75V LONGITUDINAL BALANCE 58dB 53dB TEMP. RANGE oC 0 to 75 -40 to 85 PACKAGE 28 Ld PLCC 28 Ld PLCC 28 Ld PLCC 28 Ld PLCC PACKAGE NO. N28.45 N28.45 N28.45 N28.45
* * * * *
*
* *
-40 to 85 -40 to 85
Device Operating Modes
MODE Low Power Standby (LPS) Forward Active (FA) Unused Reverse Active (RA) Ringing Forward Loop Back (FLB) F2 0 0 0 0 1 1 F1 0 0 1 1 0 0 1 1 F0 0 1 0 1 0 1 0 1 DET SHD SHD n/a SHD RTD SHD SHD n/a DESCRIPTION MTU compliant on hook operating mode. MTU compliant and OHT capable on hook mode, off hook loop feed mode. Reserved for internal purposes. Signalling mode which reverses direction of loop current, otherwise like Forward Active. Signalling mode used to generate high voltage balanced ringing signal. Internal loop back mode which connects internal load across Tip and Ring terminals. Signalling mode sets Tip to high impedance state, Ring output still active. Loop disconnect mode which forces both Tip and Ring to high impedance.
Tip Open/Ground Start (TO) 1 Power Denial (PD) 1
Pinout
ISL5586 (PLCC) TOP VIEW
BGND
RING
VBH
VBL
4 BSEL F2 F1 F0 DET VRSP VRSM 5 6 7 8 9 10 11 12 VTXP
3
2
1
28
27
RD
26 25 RTD 24 CDCM 23 CDCP 22 VCC 21 TL 20 VFB 19 -IN
13 VTXM
14 AGND
15 POL
16 VRXP
17 VRXM
18 VZO
4-2
ILIM
TIP
ISL5586
Absolute Maximum Ratings TA = 25oC
Maximum Supply Voltages VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +7V VCC - VBAT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110V ESD (Human Body Model) . . . . . . . . . . . . . . . . . . . . . . . . . . 500V Maximum Tip/Ring Negative Voltage Pulse (Note 7) . . . . . .VBH-15V Maximum Tip/Ring Positive Voltage Pulse (Note 7). . . . . . . . . . + 8V
Thermal Information
Thermal Resistance (Typical, Note 1) JA (oC/W) PLCC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Maximum Junction Temperature Plastic . . . . . . . . . . . . . . . . .150oC Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC (PLCC - Lead Tips Only)
Operating Conditions
Temperature Range Industrial. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to 85oC Positive Power Supply (VCC). . . . . . . . . . . . . . . . . . . . . . . . . . . .+5V Negative Power Supply (VBH, VBL). . . . . . . . . . . . . . -100V to -24V
Die Characteristics
Substrate Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -VBH Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bipolar-DI
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE: 1. JA is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details. Electrical Specifications Unless Otherwise Specified, TA = -40oC to 85oC, VBL = -24V, VBH = -100V, VCC = +5V, AGND = BGND = 0V, loop current limit = 25mA. All AC Parameters are specified at 600, 2-wire terminating impedance over the frequency band of 300Hz to 3.4kHz. Protection resistors = 0. These parameters apply generically to each product offering. TEST CONDITIONS MIN 35 10 VRS to 2-Wire, RLOAD = 5 REN RL = 1.3 k, VT-R = |VBH| -5 Forward Active Mode, Referenced to VRS Input. Ringing Mode Referenced to the Differential Ringing Amplitude. Tip, Referenced to VBH/2 + 0.5V Ring, Referenced to VBH/2 + 0.5V AC TRANSMISSION PARAMETERS Receive Input Impedance, VRXP (Note 2) Receive input Impedance, VRXM (Note 2) Transmit Output Impedance (Note 2) Transmit Output Drive Capability (Note 2) 4-Wire Port Overload Level 2-Wire Port Overload Level 2-Wire Return Loss (Note 2) Longitudinal Current Capability per Wire (Note 2) 2-Wire Longitudinal Balance (ON-Hook and OFF-Hook) (Notes 4, 5) 4-Wire Longitudinal Balance (ON-Hook and OFF-Hook) (Notes 4, 5) 4-Wire to 2-Wire Insertion Loss 2-Wire to 4-Wire Insertion Loss 4-Wire to 4-Wire Insertion Loss DC Current Capacitance to Ground THD = 1% THD = 1% 200Hz f 1kHz 1kHz f 3.4kHz False Detect False Detect in Low Power Standby 200Hz, 500Hz, 1000Hz 3000Hz 200Hz, 500Hz, 1000Hz 3000Hz 0dBmo at 1kHz 0dBmo at 1kHz 0dBmo at 1kHz 379 100 0.30 3.1 3.1 20 10 58 53 58 53 2.72 -0.2 2.72 -0.15 -0.15 541 142 0.01 1.0 1.0 3.5 3.5 35 23 61 61 64 62 2.92 0 2.92 0.03 0.03 100 3.12 0.2 3.12 0.15 .15 k k mA pF VPEAK VPEAK dB dB mA RMS mARMS dB dB dB dB dB dB dB dB dB -3.0 -3.0 TYP 99.5 0.8 100 100 0.2 0.2 MAX 5 3.0 3.0 UNITS M M V/V % dB dB V V
PARAMETER RINGING PARAMETERS VRSP Input Impedance (Note 2) VRSM input impedance (Note 2) Differential Ringing Gain (Note 3) Ringing voltage Total Distortion 4-Wire to 2-Wire Ringing Off Isolation 2-Wire to 4-Wire Transmit Isolation Centering Voltage Accuracy
Frequency Response, On Hook, 2-Wire to 4-Wire, 4-Wire Referenced to 0dBmo at 1004Hz, to 2-Wire, 4-Wire to 4-Wire 400Hz f 2800Hz Frequency Response, Off Hook 2-Wire to 4-Wire, 4-Wire to 2-Wire, 4-Wire to 4-Wire Referenced to 0dBmo at 1004Hz, f = 400Hz, 2800Hz
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ISL5586
Electrical Specifications Unless Otherwise Specified, TA = -40oC to 85oC, VBL = -24V, VBH = -100V, VCC = +5V, AGND = BGND = 0V, loop current limit = 25mA. All AC Parameters are specified at 600, 2-wire terminating impedance over the frequency band of 300Hz to 3.4kHz. Protection resistors = 0. These parameters apply generically to each product offering. (Continued) TEST CONDITIONS MIN 33 27 22 28 40 43 44 -8.5 15 -10 40 13.5 43 43 5 Assumes 1% External Programming Resistor -10 2.3 -10 IC Junction Temperature 2.0 VIL = 0.4V VIL = 0.4V VIH = 2.4V IOL = 5mA IOH = 100A 2.4 TYP 0.02 0.05 0.10 0.01 45 40 29 45 50 50 62 10.0 10.0 1.0 24 7.0 14.5 48 51 -53 -52 1.0 2.60 175 7.5 1.0 0.01 0.15 3.2 3.2 0.65 5.0 1.5 MAX 13.0 13.0 +8.5 45 +10 100 16.5 -56 -56 52 15 +10 2.9 +10 0.8 20 0.4 3.5 5.0 0.9 6.5 2.5 UNITS dB dB dB dB dB dB dB dB dB dB dB dBrnc dBrnc % mA % mA mA VDC VDC VDC VDC VDC VDC V mA % % V %
oC
PARAMETER
Amplitude Tracking, Off Hook, 2-Wire to 4-Wire, 4-Wire to +3dBmo to -37dBmo, f = 1004Hz, 2-Wire, 4-Wire to 4-Wire Referenced to 0dBmo -37 to -50dBmo -50 to -55dBmo Amplitude Tracking, ON-Hook Signal to Distortion, 2-Wire to 4-Wire, 4-Wire to 2-Wire, 4-Wire to 4-Wire, ON-Hook and OFF-Hook Signal Frequency Distortion (0Hz to 12kHz) Single Frequency Distortion (0Hz to 4kHz) Intermodulation Distortion, 2-Wire to 4-Wire, 4-Wire to 2-Wire, 4-Wire to 4-Wire (IEEE Standard 743-1984) Idle Channel Noise, 2-Wire (Note 5) Idle Channel Noise, 4-Wire (Note 5) DC PARAMETERS OFF-Hook Loop Current Limit OFF-Hook Transient Current Limit Loop Current During Low Power Standby Open Circuit Voltage (|Tip - Ring|) Forward and Reverse Active modes Open Circuit Voltage (|Tip-Ring|) LPS Absolute Open Circuit Voltage (Relative to GND) Absolute Open Circuit Voltage TEST ACCESS FUNCTIONS Loopback Max Battery LOOP DETECTORS AND SUPERVISORY FUNCTIONS Switch Hook Programming Range Switch Hook Programming Accuracy Dial Pulse Distortion Ring Trip Comparator Threshold Ring Trip Programming Current Accuracy Thermal Shutdown Threshold LOGIC INPUTS (F0, F1, F2, BSEL) Input Low Voltage Input High Voltage Input Low Current (F0, F1, F2) Input Low Current (BSEL) Input High Current (F0, F1, F2, BSEL) LOGIC OUTPUT (DET) Output Low Voltage Output High Voltage SUPPLY CURRENTS Low Power Standby, BSEL = 2.0V, VBH = -75V to -100V ICC IBH Forward or Reverse, BSEL =.8V ICC IBL Programming Accuracy (1% External Resistor) Programming Range Programming Accuracy Programming Range Forward Polarity Only (R L = 600) VBL = -16V VBL = -24V VBH > -60V VBH > -60V VRG in FA, VTG in RA, VBH > -60V VRG in LPS 0dBmo to -37dBmo, f = 1004Hz, Referenced to 0dBmo Input level 0dBmo to -30dBmo Input Level -30 to -40dBmo Input Level -40 to -45dBmo 0dBmo input, 0 Hz f 12kHz 0dBmo Input, 1004Hz f 1024Hz 4-Tone Second-Order Intermodulation Products 4-Tone Third-order Intermodulation Products C-Message, Forward Active, Low Battery Enabled C-Message, Forward Active, Low Battery Enabled
V V A A A V V mA mA mA mA
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ISL5586
Electrical Specifications Unless Otherwise Specified, TA = -40oC to 85oC, VBL = -24V, VBH = -100V, VCC = +5V, AGND = BGND = 0V, loop current limit = 25mA. All AC Parameters are specified at 600, 2-wire terminating impedance over the frequency band of 300Hz to 3.4kHz. Protection resistors = 0. These parameters apply generically to each product offering. (Continued) TEST CONDITIONS ICC IBL IBH Forward Active, BSEL = 2.0V, VBH = -85V ICC IBL IBH Forward Active, BSEL = 2.0V, VBH = -75V ICC IBL IBH Ringing, BSEL = 2.0V, VBH = -100V ICC IBL IBH Ringing, BSEL = 2.0V, VBH = -85V ICC IBL IBH Ringing, BSEL = 2.0V, VBH = -75V ICC IBL IBH Forward Loopback, BSEL = 0.8V, VBL = -24V Tip Open, BSEL = 2.0V Power Denial, BSEL = 0.8V or 2.0V ON HOOK POWER DISSIPATION (Note 6) Forward or Reverse Low Power Standby VBL = -24V VBH = -100V VBH = -85V VBH = -75V Ringing VBH = -100V VBH = -85V VBH = -75V OFF HOOK POWER DISSIPATION (Note 6) Forward or Reverse POWER SUPPLY REJECTION RATIO V CC to 2-Wire, BSEL = 0.8V f = 50kHz f = 300Hz f 3400Hz f = 8kHz f 16kHz VCC to 4-Wire, BSEL = 0.8V f = 50Hz f = 300Hz f 3400Hz f = 8kHz f 16kHz VBL to 2-Wire, BSEL = 0.8V f = 50Hz f = 300Hz f 3400Hz f = 8kHz f 16kHz VBL to 4-Wire, BSEL = 0.8V f = 50Hz f = 300Hz f 3400Hz f = 8kHz f 16kHz VBH to 2-Wire, BSEL = 2.0V f = 50Hz f = 300Hz f 3400Hz f = 8kHz f 16kHz 50 45 28 70 55 40 25 38 28 27 36 23 27 35 23 dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB VBL = -24V, ILIM = 25mA, RL = 300 305 mW 57 83 70 64 294 236 206 mW mW mW mW mW mW mW ICC IBL ICC IBL ICC IBL MIN TYP 7.0 1.4 1.8 6.6 1.35 1.60 6.3 1.25 1.45 7.4 1.5 2.2 6.80 1.36 2.1 6.4 1.26 2.0 10.3 23.0 3.2 0.1 3.4 0.22 MAX 9.0 2.0 3.0 8.5 2.0 2.75 8.0 2.0 2.5 10.0 2.0 3.0 9.25 2.0 3.0 8.5 2.0 3.0 13.5 32.0 6.0 0.50 UNITS mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA
PARAMETER Forward Active, BSEL = 2.0V, VBH = -100V
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ISL5586
Electrical Specifications Unless Otherwise Specified, TA = -40oC to 85oC, VBL = -24V, VBH = -100V, VCC = +5V, AGND = BGND = 0V, loop current limit = 25mA. All AC Parameters are specified at 600, 2-wire terminating impedance over the frequency band of 300Hz to 3.4kHz. Protection resistors = 0. These parameters apply generically to each product offering. (Continued) TEST CONDITIONS f = 50Hz f = 300Hz f 3400Hz f = 8kHz f 16kHz NOTES: 2. These parameters are controlled via design and Statistical Process Control and are not directly tested. These parameters are characterized upon initial design release and upon design changes which would affect these characteristics. 3. Input voltage = 0.636VRMS for VBH = -100V, 0.530VRMS for VBH = -85V and 0.460VRMS for -75V devices. 4. Tested per IEEE455-1985, with 368 resistors connected to the Tip and Ring terminals. 5. These parameters are tested 100% at room temperature, and are guaranteed but not tested across the full temperature range via statistical characterization and design. 6. The power dissipation is based on actual device measurements and will be less than worst case calculations based on data sheet supply current limits. 7. Characterized with 2 x 10us and 10 x 1000us first level lightning surge waveform (GR-1089-CORE). MIN TYP 76 55 42 MAX UNITS dB dB dB
PARAMETER VBH to 4-Wire, BSEL = 2.0V
Design Equations
Refer to Figure 14 for programming resistor connections.
Loop Supervision Thresholds
SWITCH HOOK DETECT The desired switch hook detect threshold current (ISH) is set by a single external resistor, RSH as follows
R SH = 615 I SH (EQ. 1)
illustrated in Figure 1, a complex programming network is required. RESISTIVE IMPEDANCE SYNTHESIS The AC source resistance of the SLIC is synthesized with a single external resistor RS as follows:
400 R S = Z0 x --------- = 133.3 ( Z0 ) 3 - (EQ. 4)
The loop current threshold programming range is from 5mA to 15mA. RING TRIP DETECT The ring trip detect threshold (IRT) is set by a single external resistor, R RT as follows.
R R T = 1800 I R T (EQ. 2)
The synthesized resistance (Z0) is determined by the characteristic line resistance and protection resistors as shown in Equation 5.
Z O = R L - ( RP 1 + RP 2 ) (EQ. 5)
COMPLEX IMPEDANCE SYNTHESIS A complex network is used in place of RS when the termination impedance of the line is complex as shown in Figure 1.
2-WIRE TERMINATION IMPEDANCE (ZL) C2 R1 R2 PROGRAMMING NETWORK (ZS) CP RS RP
IRT should be set between the peak ringing current and the peak off hook current while still ringing. In addition, the ring trip current must be set below the transient current limit including tolerances. The ringing signal filter capacitor C RT, in parallel with RRT sets the ring trip response time. LOOP CURRENT LIMIT The DC loop current limit (ILIM ) is programmed by the external resistor RIL as follows.
1760 R IL = -----------ILI M (EQ. 3)
FIGURE 1. COMPLEX PROGRAMMING NETWORK
The loop current limit programming range is from 15mA to 45mA.
The component R S has a different design equation than the RS used for resistive impedance synthesis. The design equations for each component are provided below where RP1 and RP2 are the protection resistors and RP is a component of the programming network.
R S = 133.3 x ( R1 - RP 1 - RP 2 ) R P = 133.3 x R 2 C P = C 2 133.3 (EQ. 6) (EQ. 7) (EQ. 8)
Impedance Matching
The AC source impedance of the SLIC is programmed with the external impedance network ZS as described next. To synthesize and match Resistive line terminations the programming network is simply a resistor (RS) as shown in Figure 14. For complex line terminations such as the one
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ISL5586
Z O = ( R1 - RP1 - RP2 ) + R2 C2 (EQ. 9)
4-WIRE TO 2-WIRE GAIN The 4-wire to 2-wire gain (G42) is defined as the receive gain. It is a function of the terminating impedance, synthesized impedance and protection resistors. The gain is defined from the Receive input terminals (VRXP, VRXM) to the terminating impedance (ZL) on the 2-wire side, and is illustrated in Figure 12.
ZL G 42 = - 2.8 ----------------------------------------- Z O + 2R P + Z L
For example, a source current limit setting of 50mA is programmed with a 35.6k resistor connected from pin 16 of the device to ground. This setting determines the maximum amount of current which flows from Tip to Ring during an off hook event until the DC loop current limit responds. In addition this setting also determines the amount of current which will flow from Tip or Ring when external battery faults occur. SINK CURRENT PROGRAMMING The sink current limit is internally offset 20% higher than the externally programmed source current limit setting.
I SN K = 1.20 x I SRC (EQ. 14)
(EQ. 10)
When the device source impedance and the protection resistors equal the terminating impedance, the receive gain equals 2.92dB and is inverted with respect to the input. 2-WIRE TO 4-WIRE GAIN The 2-wire to 4-wire gain (G24) is the gain from tip and ring to the transmit differential output. The transmit gain is given by Equation 11. Note that VTR is defined on the line side of the protection resistors (reference Figure 13). With ZL set to 600 ohms, the protection resistors set to 50/terminal and Z0 = ZL-2RP the Transmit gain equals -0.833 (-1.59dB) and is inverted with respect to the 2-wire input (VTR ).
ZO G 24 = - 2 ----------------------------------------- Z O + 2R P + ZL (EQ. 11)
If the source current limit is set to 50mA, the sink current limit will be 60mA. This setting will determine the amount of current which flows into Tip or Ring when external ground faults occur. FUNCTIONAL DESCRIPTION Each amplifier is designed to limit source current and sink current. The diagram below shows the functionality of the circuit for the case of limiting the source current. A similar diagram applies to the sink current limit with current polarity changed accordingly.
IO/K IREF = 1.21/TL I ERR 200K
TRANSHYBRID GAIN The transhybrid gain is defined as the 4-wire to 4-wire gain (G 44) and is given by Equation 12 (Reference Figure 14)).
ZO G 44 = - 2.8 -------------------------------------- Z O + 2 RP + Z L (EQ. 12) FIGURE 2. CURRENT LIMIT FUNCTIONAL DIAGRAM
+ ISIG VB/2 20 TIP or RING IO
Transient Current Limit
The drive current capability of the output amplifiers is determined by an externally programmable output current limit circuit which is separate from the DC loop current limit function. The transient current limit is programmed with a resistor to ground at the TL pin. The current limit circuit works in both the source and sink direction, with an internally fixed offset to prevent the current limit functions from turning on simultaneously. The current limit function is provided by sensing line current and reducing the voltage drive to the load when the externally set threshold is exceeded, hence forcing a constant source or sink current. SOURCE CURRENT PROGRAMMING The source current is externally programmed as shown in Equation 13.
1780 R TL = ------------ISRC (EQ. 13)
During normal operation, the error current (IERR) is zero and the output voltage is determined by the signal current (ISIG) multiplied by the 200K feedback resistor. With the current polarity as shown for ISIG, the output voltage moves positive with respect to half battery. Assuming the amplifier output is driving a load at a more negative potential, the amplifier output will source current. During excessive output source current flow, the scaled output current (IO /K) exceeds the reference current (IREF) forcing an error current (IERR). With the polarity as shown the error current subtracts from the signal current, which reduces the amplifier output voltage. By reducing the output voltage the source current to the load is decreased and the output current is limited. DETERMINING THE PROPER SETTING Since this feature programs the maximum output current of the device, the setting must be high enough to allow for detection of ring trip or programmed off hook loop current, whichever is greater.
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ISL5586
To allow for proper ring trip operation, the transient current limit setting should be set at least 25% higher than the peak ring trip current setting. Setting the transient current 25% higher should account for programming tolerances of both the ring trip threshold and the transient current limit.
TIP GND 600 TIP AMP
If loop current is larger than ring trip current (low REN applications) then the transient current limit should be set at least 35% higher than the loop current setting. The slightly higher offset accounts for the slope of the loop current limit function. Attention to detail should be exercised when programming the transient current limit setting. If ring trip detect does not occur while ringing, then re-examine the transient current limit and ring trip threshold settings.
RING RING AMP 600 MTU REF
FIGURE 3. LPS 2-WIRE INTERFACE CIRCUIT DIAGRAM
MTU Compliance
Maintenance Termination Unit or MTU compliance places DC voltage requirements on the 2-wire terminals during idle line conditions. The minimum idle voltage for compliance is 42.75V. The high side of the MTU range is 56V. The voltage is expressed as the difference between Tip and Ring. The Tip voltage is held near ground through a 600 resistor and switch. The Ring voltage is nominally limited to -49V by the MTU reference. A switch and 600 resistor connect the MTU reference to the Ring terminal. When the high battery voltage exceeds the MTU reference of -49V, the Ring terminal will be clamped by the internal reference. The same Ring relationships apply when operating from the low battery. For operating battery voltages (VBH) less than or equal to the internal MTU reference, the Ring voltage will be approximately 4.5 volts more positive than VBH .
Low Power Standby Mode
Overview
The low power standby mode (LPS, 000) should be used in conjunction with the high battery during idle line conditions. The SLIC is designed to operate from the high battery during this mode so MTU compliance can be met. Most of the internal circuitry is powered down, resulting in low power dissipation. If MTU compliance is not required during idle line conditions, the device may be operated from the low battery which will decrease the standby power dissipation.
TABLE 1. DEVICE INTERFACES DURING LPS INTERFACE Receive Ringing Transmit 2-Wire Loop Detect ON x x OFF x x x Amplifiers disabled. Switch hook. NOTES AC transmission, impedance matching and ringing are disabled during this mode.
Loop Current
In the LPS mode, the device is capable of providing DC current to a load through a path of resistors and switches. The current available for switch hook detect is a function of the off hook loop resistance (R LOOP). This includes the off hook phone resistance and copper loop resistance. The current available during LPS is given by Equation 15.
I LOOP = ( - 1 - ( - 49 ) ) ( 600 + 600 + R LOOP ) (EQ. 15)
2-Wire Interface
In the LPS mode, the 2-wire interface is maintained with internal switches, resistors, and voltage references. The Tip and Ring amplifiers are turned off to conserve power. The device will provide MTU compliance, loop current, and loop supervision. Figure 2 represents the internal circuitry providing the 2-wire interface when in this mode of operation.
Internal current limiting of the standby switches will limit the maximum current to approximately 23mA. The longitudinal current capability is guaranteed to be greater than or equal to 10mARMS per pin. When longitudinal currents exceed this level, false off hook detection may occur. The reduction in longitudinal current capability with respect to the Forward Active mode is a result of turning off the Tip and Ring amplifiers.
On Hook Power Dissipation
The on hook power dissipation of the SLIC in the LPS mode is determined by the operating voltages and quiescent currents and is calculated below.
P LPS = V BH x I BH Q + V BL x I BLQ + V C C x ICC Q (EQ. 16)
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ISL5586
The quiescent current terms are specified in the electrical tables for each operating mode. Load power dissipation is not a factor since this is an on hook mode. Some applications may specify a standby current. The standby current may be a charging current required for modern telephone electronics.
RB RCS VOUT RL RA VIN
+
RC
Standby Current Power Dissipation
Any standby line current, ISLC , introduces an additional power dissipation term PSLC . Equation 17 illustrates the power contribution is zero when the standby line current is zero.
P SLC = ISLC x ( V BH - 49 + 1 + I SLC x1200 ) (EQ. 17)
-
+ KS
FIGURE 4. VOLTAGE FEED CURRENT SENSE DIAGRAM
If the battery voltage is less than -49V (the MTU clamp is off), the standby line current power contribution reduces to Equation 18.
P SLC = ISLC x ( V BH + 1 + ISLC x1200 ) (EQ. 18)
By monitoring the current at the amplifier outputs, a negative feedback mechanism sets the output voltage for a defined load. The amplifier closed loop gains are set by internal resistor ratios (R A , RB , RC) providing all the performance benefits of matched resistors. The internal sense resistor RCS , is much smaller than the gain resistors and are typically 20. The feedback mechanism, KS , represents the gain configuration providing negative feedback to the loop.
Most applications do not specify charging current requirements during standby. When specified, the typical charging current may be as high as 5mA.
DC Loop Feed
The feedback mechanism for monitoring the DC portion of the loop current is contained within the loop detector block. A low pass filter is used in the feedback loop to block voice and other signals from interfering with the loop current limit function. The pole of the low pass filter is set by the external 4.7F capacitor (CDC) and an internal 8K resistor. The DC feed characteristic of the SLIC will drive Tip and Ring towards half battery to regulate the DC loop current. For light loads, Tip will be near -4V and Ring will be near VVBL + 4.5V. Most applications will operate the device from low battery while off hook. The following diagram depicts the DC feed characteristic.
VTR(OC) m = (VTR/IL) = 11.1k
Forward Active Mode
Overview
The Forward Active mode (FA, 001) is the primary AC transmission mode of the SLIC. On hook transmission, DC loop feed and voice transmission are supported during this mode. The device may be operated from either high or low battery for on-hook transmission and from low battery for loop feed. Loop supervision is provided by the switch hook detector at the DET output. When DET goes low, the low battery should be selected for DC loop feed and voice transmission.
On-Hook Transmission
The primary purpose of on hook transmission will be to support caller ID and other advanced signalling features. The transmission over load level while on hook is 3.1V PEAK . When operating from the high battery, the DC voltages at Tip and Ring are MTU compliant. The typical Tip voltage is -4V and the Ring voltage is a function of the battery voltage for battery voltages less than -60V as shown in Equation 19.
V RING = V BH + 4.5V (EQ. 19)
VTR , DC (V)
ILOOP (mA)
ILIM
FIGURE 5. DC FEED CHARACTERISTIC
The point on the y-axis labeled VTR(OC) is the open circuit Tip to Ring voltage and is defined by the feed battery voltage.
V TR ( OC ) = VBL - 9 (EQ. 20)
Feed Architecture
The SLIC design implements a voltage feed current sense architecture. The voltage across Tip and Ring is controlled by sensing the load current. Resistors are placed in series with the Tip and Ring outputs to provide the current sensing function. The diagram below illustrates the concept.
The curve of Figure 5 shows the loop current for a given set of loop conditions. The loop conditions are determined by the low battery voltage and the DC loop resistance. The DC loop resistance is the sum of the protection resistance, copper resistance (ohms/foot) and the telephone off hook DC resistance.
4-9
ISL5586
ISC ILIM ILOOP (mA) IA IB
Since the current relationships are different for constant current versus constant voltage, the region of device operation is critical to valid power dissipation calculations.
Reverse Active Mode
Overview
2RP RLOOP () RKNEE
FIGURE 6. ILOOP VERSUS R LOOP LOAD CHARACTERISTIC
The slope of the feed characteristic and the battery voltage define the maximum loop current on the shortest possible loop as the short circuit current ISC .
V TR ( OC ) - 2R P I LIM I SC = ILI M + ----------------------------------------------------1.1e 4 (EQ. 21)
The reverse active mode (RA, 011) provides the same functionality as the forward active mode. On hook transmission, DC loop feed, and voice transmission are supported. Loop supervision is provided by the switch hook detector. The device may be operated from either high or low battery. When in the Reverse Active mode the Tip and Ring DC voltage characteristics exchange roles. That is, Ring is typically 4V below ground and Tip is typically 4.5V more positive than battery.
The term ILIM is the programmed current limit, 1760/RIL. The line segment IA represents the constant current region of the loop current limit function.
VTR ( OC ) - R LOOP I LIM I A = I LIM + ------------------------------------------------------------1.1e4
Silent Polarity Reversal
Changing from forward active to reverse active or vice versa is referred to as polarity reversal. Many applications require control of the polarity reversal transition time. Requirements range from minimizing cross talk to protocol signalling. The SLIC uses an external low voltage capacitor, CPOL , to set the reversal time. The capacitor is isolated from the AC loop so that loop stability is not influenced by its selection. Once CPOL is set, the reversal time will remain nearly constant over various load conditions. The internal circuitry used to set the polarity reversal time is shown in Figure 7. During Forward Active the switch is open and the current from source I1 charges the external timing capacitor CPOL. The internal resistor provides a clamping function for the voltage at the POL node. When the Reverse Active mode is initiated the switch closes and the difference current (I2-I1) discharges the timing capacitor. The voltage at the POL node drives one side of a transistor differential pair which forces the Forward or Reverse condition on the Tip and Ring amplifiers. The forward/reverse transition time is given by Equation 28, where time is the required reversal time.
time C POL = --------------75000 (EQ. 28)
(EQ. 22)
The maximum loop resistance for a programmed loop current is defined as R KNEE .
V TR ( OC ) R KNEE = ----------------------ILIM
(EQ. 23)
When RKNEE is exceeded, the device will transition from constant current feed to constant voltage, resistive feed. The line segment IB represents the resistive feed portion of the load characteristic.
V TR ( OC ) I B = ----------------------R LOOP (EQ. 24)
Power Dissipation
The power dissipated by the SLIC in the Forward Active mode while on hook is strictly a function of the quiescent currents for each supply.
+ VBL x I BLQ + VCC x ICCQ P FAQ = V BH x I BH Q
(EQ. 25)
Off hook power dissipation is increased above the quiescent power dissipation by the DC load. If the loop length is less than or equal to R KNEE , the device is providing constant current (IA) , and the power dissipation is calculated using Equation 26.
P FA ( IA ) = PFA ( Q ) + ( V BL xI A ) - ( R LOOP xI 2 A ) (EQ. 26)
Polarized capacitors may be used for CPOL. The low voltage at the POL pin and minimal voltage excursion in the order of 0.75V, are well suited for polarized capacitors.
If the loop length is greater than RKNEE , the device is operating in the constant voltage, resistive feed region. The power dissipated in this region is calculated using Equation 27.
P FA ( IB ) = PFA ( Q ) + ( V BL xI B ) - ( R LOOP xI 2 B ) (EQ. 27)
4-10
ISL5586
VBH V R = ----------- - ( 50 x V DIF ) 2 (EQ. 30)
I1 POL
75k I2
CPOL
When the differential input signal is zero, the Tip and Ring amplifier outputs are centered at half battery. The device provides auto centering for easy implementation of sinusoidal ringing waveforms. Both AC and DC control of the Tip and Ring outputs is available during ringing. This feature allows for DC offsets as part of the ringing waveform.
FIGURE 7. REVERSAL TIMING CONTROL
Ringing Input Terminals Power Dissipation
The power dissipation equations for forward active operation also apply to the reverse active mode. The differential terminals feature high input impedance which allows the use of low value capacitors for AC coupling the ring signal if necessary. The Ringing input is enabled only during the ringing mode, therefore a free running oscillator may be connected at all times. When operating from a battery of -100V, each amplifier, Tip and Ring, will swing a maximum of 95VP-P . Hence, the maximum differential signal swing between VRSP and VRSM to achieve full scale ringing is approximately 1.9VP-P .
Ringing
Overview
The Ringing mode (RNG, 100) provides linear amplification to support a variety of ringing waveforms. A programmable ring trip function provides loop supervision and auto disconnect upon ring trip. The device is designed to operate from the high battery during this mode.
Logic Control
Ringing patterns consist of silent and ringing intervals. The ringing to silent pattern is called the ringing cadence. During the silent portion of ringing, the device can be programmed to any other operating mode. The most likely candidates are low power standby or forward active. Depending on system requirements, the low or high battery may be selected. Loop supervision is provided with the ring trip detector. The ring trip detector senses the change in loop current when the phone is taken off hook. The loop detector full-wave rectifies the ringing current, which is then filtered with external components RRT and CRT. The resistor RRT sets the trip threshold and the capacitor CRT sets the trip response time. Most applications will require a trip response time less than 150ms. Three very distinct actions occur when the device detects a ring trip. First, the DET output is latched low. The latching mechanism eliminates the need for software filtering of the detector output. The latch is cleared when the operating mode is changed externally. Second, the Ringing inputs are disabled, removing the ring signal from the line. Third, the device is internally forced to the forward active mode.
Architecture
The SLIC provides linear amplification to the differential signal applied to the ringing inputs (VRSP, VRSM ). The differential ringing gain of the device is 100V/V. The circuit model for the ringing path is shown in Figure 8.
R 20 TIP 5:1 RING 20 + + VBH 2 1.25R + R/8 +
VRSM + 1.25R
-
R R +
R
VRSP
FIGURE 8. LINEAR RINGING MODEL
-
-
Power Dissipation
The voltage gain from the differential ringing input to the Tip output is 50V/V. The resistor ratios provide a gain of 10 and the current mirror provides a gain of 5. The voltage gain from the differential input to the Ring output is -50V/V. The equations for the Tip and Ring outputs during ringing are provided below.
V BH V T = ----------- + ( 50 x VD IF ) 2 (EQ. 29)
The power dissipation during ringing is dictated mostly by the load driving requirements and the ringing waveform. The key to valid power calculations is the correct definition of average and RMS currents. The average current defines the high battery supply current. The RMS current defines the load current. The cadence provides a time averaging reduction in the peak power. The total power dissipation consists of ringing power, Pr, and the silent interval power, Ps .
tr ts P R NG = Pr x ------------- + P s x ------------t +t t +t
r s r s
(EQ. 31)
4-11
ISL5586
The terms tR and tS represent the cadence. The ringing interval is tR and the silent interval is tS . A typical cadence ratio tR :tS is 1:2. The quiescent power of the device in the Ringing mode is defined in Equation 32.
P r ( Q ) = VBH x I BHQ + VBL x I BLQ + VCC x I CCQ (EQ. 32)
AC Verification
The entire AC loop of the device is active during the forward loop back mode. Therefore a 4-wire to 4-wire level test capability is provided. Depending on the transhybrid balance implementation, test coverage is provided by a one or two step process. System architectures which cannot disable the transhybrid function would require a two step process. The first step would be to send a test tone to the device while on hook and not in forward loop back mode. The return signal amplitude would be the test signal amplitude times the gain of the transhybrid amplifier. Since the device would not be terminated in the on hook mode, cancellation would not occur. The second step would be to program the device to FLB mode and resend the test tone. The return signal would be much lower in amplitude than the first step, indicating the device was active and the internal termination attenuated the return signal. System architectures which can disable the transhybrid function would achieve test coverage with a signal step. Once the transhybrid function is disabled the SLIC can be programmed to the FLB mode and the test tone can be sent. The return signal level is determined by the 4-wire to 4-wire gain of the SLIC times the amplitude of the signal sent.
The total power during the ringing interval is the sum of the quiescent power and loading power:
VRMS P r = Pr ( Q ) + VBH x IAVG - ----------------------------------------Z +R
REN 2
(EQ. 33)
LOOP
For sinusoidal waveforms, the average current, IAVG, is defined in Equation 34.
V RMS x 2 2 I AVG = -- ---------------------------------------- Z REN + R LOOP (EQ. 34)
The silent interval power dissipation will be determined by the quiescent power of the selected operating mode.
Forward Loop Back Mode
Overview
The Forward Loop Back mode (FLB, 101) provides test capability for the SLIC. An internal signal path is enabled allowing for both DC and AC verification by the connection of an internal 600 ohm resistor across Tip and Ring. This internal terminating resistor has a tolerance of 10% at room temperature. The device is intended to operate from only the low battery during this mode.
Tip Open/Ground Start Mode
Overview
The Tip Open mode (TO, 110) is intended for compatibility with PBX type interfaces. The device does not provide transmission capability in this mode which is intended for idle line conditions. Loop supervision is provided by the switch hook detector and either high or low battery operation is supported.
Architecture
When the forward loop back mode is initiated internal switches connect a 600 load across the outputs of the Tip and Ring amplifiers as shown below.
Functionality
During Tip Open operation, the Tip switch is disabled and the Ring switch is enabled. The minimum Tip impedance is 30k. The only active path through the device will be through the Ring switch. In keeping with the MTU characteristics of the device, Ring will not exceed -56V when operating from the high battery. Though MTU does not apply to Tip Open, safety requirements are satisfied.
TIP TIP AMP 600 RING AMP RING
FIGURE 9. FORWARD LOOP BACK INTERNAL TERMINATION
DC Verification
When the internal signal path is provided, DC current will flow from Tip to Ring. The DC current will force DET low, indicating the presence of loop current. In addition to verifying device functionality, toggling the logic output verifies the interface to the system controller.
4-12
ISL5586 Power Denial
Overview
The power denial mode (111) will shutdown the entire device except for the logic interface. Loop supervision is not provided. This mode may be used as a sleep mode or to shut down the SLIC in the presence of fault conditions. Switching between high and low battery will have no effect during power denial. from the low battery if MTU compliance is not required, further reducing standby power dissipation.
High Battery Operation
Other than ringing, the high battery should be used for standby conditions which must provide MTU compliance. During standby operation the power consumption is typically 85mW with -100V battery. If ringing requirements do not require full 100V operation, then a lower battery will result in lower standby power.
Functionality
During power denial, both the Tip and Ring amplifiers are disabled, presenting high impedances to the line. The voltages at both outputs are near ground.
High Voltage Decoupling
The 100V rating of the SLIC dictates a capacitor of higher voltage rating be used for decoupling. Suggested decoupling values for all device pins are 0.1F. If the protection scheme shown in Figure 15 is implemented the VBH decoupling capacitor should be increased to 0.47uF. This is done to minimize the turn-on time of the battrax device during negative surge transients. Standard surface mount ceramic capacitors are rated at 100V. For applications driven by low cost and small size, the decoupling scheme shown in Figure 10 could be implemented.
Thermal Shutdown
In the event the safe die temperature is exceeded due to a fault condition the device will automatically shut down. The thermal shutdown threshold is approximately 170C.When the device cools to a temperature below the thermal threshold it will power back up automatically. If the fault persists the part will continue to go in and out of thermal shutdown which can be observed as an oscillation on Tip or Ring. Programming power denial will shut down the device and stop the self cooling cycle.
0.22
0.22
Battery Switching
Overview
The integrated battery switch selects between high battery and low battery operation. The battery switch is controlled with the logic input BSEL. When BSEL is a logic high, the high battery (VBH) is selected. A logic low will enable the low battery (VBL). All operating modes of the SLIC will function from high or low battery, but it is strongly recommended Forward Loop Back be enabled only with the low battery.
VBL VBH ISL5586
FIGURE 10. ALTERNATE DECOUPLING SCHEME
Functionality
The logic control is independent of the operating mode decode. Independent logic control provides the most flexibility and will support all application configurations. When changing device operating states, battery switching should occur simultaneously with or prior to changing the operating mode. In most cases, this will minimize overall power dissipation and prevent glitches on the DET output. The only external component required to support the battery switch is a diode in series with the VBH supply lead. In the event that high battery is removed, the diode allows the device to transition to low battery operation.
It is important to place an external diode between the VBH pin and the decoupling capacitor. Connecting the decoupling capacitor directly to the VBH pin will degrade the reliability of the device. Refer to Figure 15 for the proper arrangement. This applies to both single and stacked and decoupling schemes. If VBL and VBH are tied together the battery switch function is overridden. In this case the external diode is not needed and the decoupling capacitor may be attached directly to VBH pin.
R TIP V2W + 20
+
-
RF 1:1 VZO
-
IL
VTR RING
20
+
-
TA +
RS -IN
-
R
4R 4R 4R 4R
3R 8K VSA
Low Battery Operation
All off hook operating conditions should use the low battery to minimize power dissipation. A typical low battery operating voltage for the SLIC is -24V, however this may be increased to support longer loop lengths or high loop current requirements. Standby conditions may also operate
CFB VFB
-
+ 3R
FIGURE 11. IMPEDANCE SYNTHESIS
4-13
ISL5586
Impedance and Gain Derivations
The feedback mechanism for monitoring the AC portion of the loop current consists of two amplifiers, the sense amplifier (SA) and the transmit amplifier (TA). The AC feedback signal is used for impedance synthesis. A detailed model of the AC feed back loop is provided below VZO feedback current. This current is fed to the Tip and Ring amplifiers and yields the relationship shown in Equation 40.
V TR = - 2 x ( Vrx - V ZO ) (EQ. 40)
The voltage V ZO, is a function of the sense amplifier output voltage V SA.
RS V Z0 = - V SA x -----------8K (EQ. 41)
Impedance Programming Resistor Derivation
The gain of the transmit amplifier, set by RS , determines the programmed resistance of the SLIC. For complex line terminations RS is replaced with a complex network ZS (Figure 1). The capacitor CFB blocks the DC component of the loop current. Figure 11 illustrates the impedance synthesis loop. Note that the ground symbols shown in Figures 11 through 14 represent AC grounds, not necessarily actual DC potentials. The receiver block provides a single-ended to differential conversion with a voltage gain of 2. The voltage at Tip and Ring due to the feedback from VZO is shown in Equation 35.
VTR = - 2 x VZO (EQ. 35)
VSA can be expressed in terms of loop current as shown in Equation 42.
3 V SA = - IL x 2 x 20 x -4 (EQ. 42)
Substituting Equation 42 into Equation 41 gives Equation 43.
RS 3 V Z0 = - IL x 2 x 20 x -- x ----------4 8K (EQ. 43)
The VZ0 term in Equation 40 can now be replaced by Equation 43 yielding Equation 44.
RS 3 - V TR = - 2 x V rx - 2 IL x 2 x 20 x -- x ------------ 4 8K (EQ. 44)
The Feedback amplifier (TA) provides the programmable gain required for impedance synthesis to the Receiver block. The output voltage (V ZO) is a function of the Sense Amplifier output voltage and the gain of the feedback amplifier, which can be substituted for VZO .
RS VTR = - 2 x VSA x ------------ 8K (EQ. 36)
A loop equation can be derived for the 2-wire side that replaces VTR as shown in the equation below.
RS 3 V 2W + IL x 2R p = - 2V rx - IL 4 x 20 x -- x ------------ 4 8K (EQ. 45)
The sense amplifier shown in Figure 11 is configured as a 4 input differential amplifier with a gain of 3/4. The output voltage, VSA , is a function of the voltage across the Tip and Ring sense resistors (20 each) which can also be expressed in terms of loop current.
V SA = - 2 x 20 x IL x ( 3 4 ) (EQ. 37)
Expressing IL in terms of V2W/ZL, rearranging, and solving for V2W yields the relationship between the 2-wire voltage and the output of the Receive amplifier.
ZL V 2W = - 2Vrx x ------------------------------------- ZL + Z 0 + 2R P (EQ. 46)
Substituting Equation 37 into Equation 35 and rearranging terms yields Z0 , the SLIC's synthesized 2-wire impedance. Rearranging and solving for RS , Equation 39 shows the relationship between the impedance programming resistor and the programmed impedance.
Rs Rs VTR 3 Z 0 = ---------- = 4 x 20 x IL x -- x ------------ = 60 x -----------4 8K IL 8K R S = 133.3 x Z 0 (EQ. 38)
The differential voice input is configured for a gain of 1.4. The relationship between VRX and the voice input is shown in Equation 47. Substituting for VRX , the 4-2-Wire gain is shown in Equation 48. Note that the differential voice input is outside the impedance synthesis loop, so the gain of the receive amplifier has no effect on the SLIC's impedance.
V rx = 1.4 x ( V R XP - V RXM ) = 1.4 x VRX4W (EQ. 47)
(EQ. 39)
ZL V 2W ------------------- = -2.8 ----------------------------------------- V RX4W Z O + 2R P + Z L
(EQ. 48)
4-WIRE TO 2-WIRE GAIN The 4-wire to 2-wire gain is defined as the gain from the differential receive input to the 2-wire load ZL. The gain is a function of the terminating impedance, synthesized impedance and protection resistors and is illustrated in Figure 12. The input current to the receiver block Irx4w comes from the difference of the VRX input current and the 4-14
When the combination of the device source impedance and the protection resistors equal the terminating impedance, the receive gain equals 2.92dB and is inverted with respect to the 4-wire input. 2-WIRE TO 4-WIRE GAIN The 2-wire to 4-wire gain (G24) is defined as the gain from the Tip and Ring terminals (VTR) to the VTX differential output.
ISL5586
Irx4w 200K RP ZL RP 20 200K 200K 1:1 20 RING + 200K 4R 4R 4R 4R + 3R 3R -IN CFB VFB VSA VRX4W + Iz0 VZO TA + R RS VRXP R VRXM 1.4R VRX 1.4R
+
TIP IL Vtr
+
+
-
V2W
-
8K
-
FIGURE 12. SCHEMATIC FOR 4-WIRE TO 2-WIRE GAIN DERIVATION
Note that in Figure 13, VTR is referenced on the line side of the protection resistors. On the 2-wire side, solving for IL in terms of V IN gives Equation 49. Equations 50 and 51 show the relationship of VIN to the outputs of the Sense Amplifier (VSA) and the Feedback Amplifier (VZ0) respectively.
V IN IL = ------------------------------------- ZL + Z + 2R P 0 V IN 3 V SA = - ------------------------------------- x 2 x 20 x -- 4 ZL + Z + 2R P 0 RS VIN 3 V Z0 = - ------------------------------------- x 2 x 20 x -- x ---------- 4 8K ZL + Z + 2R P 0 (EQ. 49)
If the combination of the protection resistors and the programmed impedance of the SLIC are equal to ZL the voltage V TR will be 1/2 VIN . The 2-wire to 4-wire gain is defined by Equation 55.
V TX4W 2Z 0 ------------------- = - ------------------------------------- V TR ZL + Z 0 + 2R P (EQ. 55)
4-WIRE TO 4-WIRE GAIN The 4-Wire to 4-Wire gain is defined in Equation 56 and is illustrated in Figure 14.The first term is identical to Equation 48.
V 2W V TX4W V TX4W ------------------- = ------------------- x ------------------V R X4W VRX4W V 2W (EQ. 56)
(EQ. 50)
(EQ. 51)
Simplifying Equation 51 in terms of Z0 gives the following equation.
VIN Z0 V Z0 = - ------------------------------------- x ---- ZL + Z 0 + 2R P 2 (EQ. 52)
The second term is derived in a similar manner as the 2-wire to 4-wire gain starting with Equation 57.
V 2W = IL x Z L (EQ. 57)
The resulting differential output voltage VTX4W , is shown in Equation 53.
V TX4W = VTXP - VTXM = VZ0 - ( - V ) = 2V Z0 Z0 (EQ. 53)
Moving around the loop from the 2-wire side to the 4-wire output we solve for VSA and VZO .
3 V 2W 3 V SA = - I L x 2 x 20 x -- = ----------- x 40 x -4 4 ZL V2W Z 0 RS V2W 3 V Z0 = ----------- x ------------ x 40 x -- = ----------- x ------ 4 ZL 8K ZL 2 (EQ. 58)
Note that the gain from VZ0 to the differential output is outside the impedance synthesis loop and will have no effect on the SLIC's programmed impedance. Substituting Equation 53 into Equation 52 and rearranging terms gives the gain from the 2-wire source (VIN ) to the differential output of the Transmit Amplifier.
Z0 V TX4W ------------------- = - ------------------------------------- VI N ZL + Z0 + 2R P (EQ. 54)
(EQ. 59)
The relationship between VZ0 and the 4-wire output is shown in Equation 53. Substituting Equation 59 into Equation 53 yields Equation 60, the second term in Equation 56.
Z0 V TX4W ------------------- = ----V2W ZL (EQ. 60)
4-15
ISL5586
Equations 48 and 60 can be combined to re-write the 4-wire to 4-wire gain equation.
ZL VTX4W Z0 ------------------- = - 2.8 ----------------------------------------- x -----V R X4W ZO + 2R P + ZL Z L (EQ. 61)
Simplifying the above yields the 4-wire to 4-wire gain.
Z0 VTX4W ------------------- = - 2.8 ----------------------------------------- V R X4W ZO + 2R P + ZL (EQ. 62)
1.4R R 200K IL ZL RP1
V
200K VRX 200K 1:1 VZO
+
1.4R R
VRXP VRXM
20
+ TIP
TR
-
VIN
+
-
RING RP2
20
+
-
TA +
RS -IN R R
VTXP + VTX4W
-
200K 4R 4R 4R 4R
3R 8K VSA
CFB VFB
-
+ 3R
-
VTXM
+
FIGURE 13. SCHEMATIC FOR 2-WIRE TO 4-WIRE GAIN DERIVATION
1.4R 200K RP1 + V2W ZL T
IL
200K VRX 200K 1:1 VZO
+ 1.4R R VRXM
-
R
VRXP + VRX4W
-
20
+ 20
-
RP2
R
+
3R
TA +
RS -IN R R
VTXP
-
200K 4R 4R 4R 4R
VTX4W + VTXM
-
8K VSA
CFB VFB
+ 3R
-
+
FIGURE 14. SCHEMATIC FOR 4-WIRE TO 4-WIRE GAIN DERIVATION
4-16
ISL5586 Pin Descriptions
PLCC 1 2 SYMBOL TIP BGND TIP Power Amplifier Output. Battery Ground - To be connected to zero potential. All loop current and longitudinal current flow from this ground. Internally separate from AGND and SGND but should be connected to the same potential as AGND & SGND. Low Battery Supply Connection. High Battery Supply Connection. Selects between high and low battery, with a logic "1" selecting the high battery and logic "0" the low battery. TTL Mode Control Input - MSB. TTL Mode Control Input. TTL Mode Control Input - LSB. Detector Output - This TTL output provides on-hook/off-hook status of the loop based upon the selected operating mode. The detected output will either be switch hook or ring trip. Non-Inverting Ringing Signal Input - Analog input for driving 2-wire interface while in Ring Mode. Inverting Ringing Signal Input - Analog input for driving 2-wire interface while in Ring Mode. Transmit Output Voltage - AC couples to CODEC. Transmit Output Voltage - AC couples to CODEC. Analog Ground Reference. This pin should be externally connected to BGND. An External Capacitor on this pin sets the polarity reversal time. Non-Inverting Analog Receive Voltage - 4-wire analog audio input voltage. Inverting Analog Receive Voltage - 4-wire analog audio input voltage. Connection Terminal for impedance matching programming resistor Connection Terminal for high pass filter capacitor and impedance matching components. Connection Terminal for high pass filter capacitor and impedance matching components. Transient Current Limit Programming Resistor Connection Terminal. Positive Voltage Power Supply, +5V +/-5%. DC Biasing Filter Capacitor - Positive Terminal. DC Biasing Filter Capacitor - Negative Terminal. Ring Trip Filter Network Connection Terminal. Loop Current Limit programming resistor connection terminal. Switch Hook Detection threshold programming resistor connection terminal. RING Power Amplifier Output. DESCRIPTION
3 4 5 6 7 8 9
VBL VBH BSEL F2 F1 F0 DET
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
VRSP VRSM VTXP VTXM AGND POL VRXP VRXM VZO -IN VFB TL VCC CDCP C DCM RTD ILIM RD RING
4-17
Basic Application Circuit
CPS1 CPS2 D1 CPS3 RP1 VBL VRXP RP2 RING VRSM RTD CR3 CP RS -IN ILIM VFB BSEL F0 F1 F2 TL DET BGND AGND 0.068F 0.068F CT2 CDCM CDC CPOL POL RTL CDCP CFB RP 100K 100K 20K CX3 SLIC_CTRL0 SLIC_CTRL1 SLIC_CTRL2 SLIC_CTRL3 SLIC_CTRL4 CT1 20K CX2 CX1 VTXM RSH RD CSH VZO VTXP VRSP CRT RRT VRXM CR2 VCC VBH TIP CR1 BCM3352 VRX0(+) VRX0(-) VTX0(+) VTX0(-) CMLEVEL RINGING_OUT(+) RINGING_OUT(-)
F1250T
4-18
ISL5586
RIL
1
3
B1100CC
2
2
B1100CC
3
1
ISL5586
F1250T
NOTE: CPS1 should be located as close as possible to the B1100CC to minimize turn-on time. Less than 2 inches is recommended. FIGURE 15. SINGLE CHANNEL INTERFACE BETWEEN ISL5586 AND BCM3352
ISL5586
TABLE 2. BASIC APPLICATION CIRCUIT COMPONENT LIST COMPONENT U1 - Ringing SLIC R TL R RT R SH R IL RS R P1,RP2 CP C RT , CPOL , CSH CFB C DC C PS1 C PS2 , CPS3 C T1, CT2 C R1, CR2, CR3 C X1, C X2, CX3 D1 D 2,D 3 R P1 , RP2 VALUE ISL5586 17.8k 22.1k 40k 71.5k 66.5k 0 Not Populated 0.47F 1.0F 4.7F 0.47F 0.1F 4.7F 3300pF 150pF 1N400X Type with Breakdown > 100V. 1N4935 Type Protection resistor values are application dependent and will be determined by protection requirements. Standard applications will use 49 per side. TOLERANCE N/A 1% 1% 1% 1% 1% 1% 20% 20% 20% 20% 20% 20% RATING N/A 0.1W 0.1W 0.1W 0.1W 0.1W 0.1W 10V 10V 10V 10V >100V 100V
Design Parameters: Ring Trip Threshold = 81mAPEAK , Switch Hook Threshold = 15mA, Loop Current Limit = 24.6mA, Synthesize Device Impedance = (3*66.5k)/400 = 498.8 , protection resistors = 50, impedance across Tip and Ring terminals = 599. Transient current limit = 100mA.
Interface Diagram
The figure 15 above shows the electrical interface between the ISL5586 and the BCM3352. Only a single channel is shown to simplify the diagram. This diagram only shows electrical interfaces and pertinent external components
the ISL5586 to the CMLEVEL of the BCM3352. Lastly, the external network attenuates the signal levels coming from the ISL5586. The ISL5586 is designed with a 2-wire to 4wire gain of 0dB and a 4-wire to 4-wire gain of +2.98dB.
Ringing Interface
The ISL5586 only passes the ringing signal on VRSP, VRSM to Tip and ring only during the ringing mode. Therefore, a single ringing generator as supplied by the BCM3352 drives all four sets of ringing inputs in the Broadcom reference design. The ISL5586 is designed with a differential ringing gain of 100V/V.
Receive Interface
The receive interface of the BCM3352 is directly coupled to the ISL5586 differential receive input. External filter capacitors are provided to minimize noise from the BCM3352. The ISL5586 is designed with a 4-wire to 2-wire gain of +2.98dB.
Transmit Interface
The differential transmit output of the ISL5586 is AC coupled to an external passive network. The external passive network accomplishes many tasks. First, it filters the noise which may exist on the CMLEVEL output of the BCM3352. Second, it biases the ground referenced output signals of
Passive Component Values
The passive component values in the Broadcom reference design may not be reflected by this document. Please refer to the Broadcom reference design documentation for the most recent schematic and COM information.
4-19
ISL5586 Plastic Leaded Chip Carrier Packages (PLCC)
0.042 (1.07) 0.048 (1.22) PIN (1) IDENTIFIER C L 0.042 (1.07) 0.056 (1.42) 0.050 (1.27) TP 0.004 (0.10) C
0.025 (0.64) R 0.045 (1.14)
N28.45 (JEDEC MS-018AB ISSUE A) 28 LEAD PLASTIC LEADED CHIP CARRIER PACKAGE
INCHES SYMBOL A MIN 0.165 0.090 0.485 0.450 0.191 0.485 0.450 0.191 28 MAX 0.180 0.120 0.495 0.456 0.219 0.495 0.456 0.219 MILLIMETERS MIN 4.20 2.29 12.32 11.43 4.86 12.32 11.43 4.86 28 MAX 4.57 3.04 12.57 11.58 5.56 12.57 11.58 5.56 NOTES 3 4, 5 3 4, 5 6 Rev. 2 11/97
D2/E2 C L E1 E D2/E2 VIEW "A"
A1 D D1 D2 E E1
D1 D 0.020 (0.51) MAX 3 PLCS
A1 A
0.020 (0.51) MIN
E2 N
SEATING -C- PLANE 0.026 (0.66) 0.032 (0.81) 0.013 (0.33) 0.021 (0.53)
0.045 (1.14) MIN VIEW "A" TYP.
0.025 (0.64) MIN
NOTES: 1. Controlling dimension: INCH. Converted millimeter dimensions are not necessarily exact. 2. Dimensions and tolerancing per ANSI Y14.5M-1982. 3. Dimensions D1 and E1 do not include mold protrusions. Allowable mold protrusion is 0.010 inch (0.25mm) per side. Dimensions D1 and E1 include mold mismatch and are measured at the extreme material condition at the body parting line. 4. To be measured at seating plane -C- contact point. 5. Centerline to be determined where center leads exit plastic body. 6. "N" is the number of terminal positions.
All Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at website www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site www.intersil.com
Sales Office Headquarters
NORTH AMERICA Intersil Corporation 2401 Palm Bay Rd. Palm Bay, FL 32905 TEL: (321) 724-7000 FAX: (321) 724-7240 EUROPE Intersil SA Mercure Center 100, Rue de la Fusee 1130 Brussels, Belgium TEL: (32) 2.724.2111 FAX: (32) 2.724.22.05 ASIA Intersil Ltd. 8F-2, 96, Sec. 1, Chien-kuo North, Taipei, Taiwan 104 Republic of China TEL: 886-2-2515-8508 FAX: 886-2-2515-8369
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